1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2008-210556, filed Aug. 19, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, gate lengths of MOS (Metal Oxide Semiconductor) transistors are shorter and shorter as semiconductor devices, such as a DRAM (Dynamic Random Access Memory), are further miniaturized. Accordingly, a great amount of substrate current flows which cannot be controlled by a gate. In other words, short-channel effects have been becoming more problematic.
In an MOS transistor used for a cell array transistor DRAM, a concentration of an impurity included in a channel region is increased to prevent such a short channel effect. However, an electric field around an S/D junction increases as a concentration of an impurity included in the channel region increases, thereby degrading refresh characteristics.
To prevent degradation of the refresh characteristics, a technology of lengthening an effective gate length by using a three-dimensional channel structure called a trench gate transistor or a recess channel transistor has been developed. Accordingly, the short channel effect can be prevented without increasing an impurity concentration, thereby preventing degradation of the refresh characteristics.
However, an increase in junction leakage current or gate voltage has been problematic though the short channel effect can be prevented.
Japanese Patent Laid-Open Publication No. 2007-158269 discloses a semiconductor device and a method of manufacturing the same. In the semiconductor device, a gate trench is formed in an active region, fin-shaped silicon thin films are formed on the sidewalls of the STI (Shallow Trench Isolation), and thereby the fin-shaped silicon thin films are used as channels in such a semiconductor device, a three-dimensional SOI channel is used as a cell array transistor, thereby decreasing the threshold voltage, enhancing the characteristics of wiring to the capacitor, and partially achieving the characteristics of a fully-depleted transistor.
However, in the method of manufacturing the three-dimensional SOI channel disclosed in the above related art, it is difficult to form the fin-shaped SOI channel with high precision and reproducibility since the fin-shaped SOI chapel is formed by processing the gate trench using a mask used for the formation of the STI. Consequently, a fluctuation in the shape of the fin-shaped SOI channel (such as in the height or width) causes a fluctuation in the transistor characteristics. Additionally, a fully-depleted fin-shaped SOI channel extending from a bottom surface of the gate trench up to a surface of a semiconductor substrate causes an increase in current flowing between the source and the drain. For this reason, it is difficult to control the threshold voltage of the transistor.